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<!@TC:1538938419>
#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 8 6.2
#Hostname: BEACONDEV3

# Mon Oct  8 02:53:39 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538938420> | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538938420> | Running in 64-bit mode 
@N: : <!@TM:1538938420> | : Running Verilog Compiler in System Verilog mode 
@N: : <!@TM:1538938420> | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_parameter.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top_define.v" (library work)
@I::"C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top.v" (library work)
<font color=#A52A2A>@W:<a href="@W:CG1337:@XP_HELP">CG1337</a> : <a href="C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top.v:194:9:194:19:@W:CG1337:@XP_MSG">gw_con_top.v(194)</a><!@TM:1538938420> | Net capture_dr is not declared.</font>
<font color=#A52A2A>@W:<a href="@W:CG1337:@XP_HELP">CG1337</a> : <a href="C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_top.v:211:9:211:23:@W:CG1337:@XP_MSG">gw_con_top.v(211)</a><!@TM:1538938420> | Net enable_i_delay is not declared.</font>
Verilog syntax check successful!
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_parameter.v:1:1:1:10:@N:CG364:@XP_MSG">gw_con_parameter.v(1)</a><!@TM:1538938420> | Synthesizing module work_C:\Gowin\1.8\IDE\data\ipcores\GAO_LITE\GW_CON\gw_con_parameter.v_unit in library work.
Selecting top level module gw_con_top

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:53:40 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538938420> | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:53:40 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:53:40 2018

###########################################################]

</pre></samp></body></html>
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<!@TC:1538938419>

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Database state : C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\synwork\|rev_1
<a name=compilerReport4></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538938422> | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:53:42 2018

###########################################################]

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<!@TC:1538938419>
Premap Report


</pre></samp></body></html>
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<!@TC:1538938419>
# Mon Oct  8 02:53:42 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport5></a>Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1538938424> | No constraint file specified. 
Linked File:  <a href="C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\ao_control_scck.rpt:@XP_FILE">ao_control_scck.rpt</a>
Printing clock  summary report in "C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\ao_control_scck.rpt" file 
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1538938424> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1538938424> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1538938424> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)

@N:<a href="@N:BN133:@XP_HELP">BN133</a> : <!@TM:1538938424> | Ignoring syn_hier=hard property on top-level design. 

Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1538938424> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1538938424> | UMR3 is only supported for HAPS-80. 
syn_allowed_resources : blockrams=10  set on top level netlist gw_con_top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)



<a name=mapperReport6></a>Clock Summary</a>
******************

          Start      Requested      Requested     Clock      Clock               Clock
Level     Clock      Frequency      Period        Type       Group               Load 
--------------------------------------------------------------------------------------
0 -       System     1123.1 MHz     0.890         system     system_clkgroup     14   
======================================================================================



Clock Load Summary
***********************

           Clock     Source     Clock Pin                        Non-clock Pin     Non-clock Pin
Clock      Load      Pin        Seq Example                      Seq Example       Comb Example 
------------------------------------------------------------------------------------------------
System     14        -          shift_dr_capture_dr_dly[0].C     -                 -            
================================================================================================


ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport7></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 14 clock pin(s) of sequential element(s)
0 instances converted, 14 sequential instances remain driven by gated/generated clocks

======================================================= Gated/Generated Clocks ========================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation                    
---------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\synwork\ao_control_prem.srm@|S:ENCRYPTED@|E:ENCRYPTED@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       ENCRYPTED           IO_port                14                     ENCRYPTED           Clock source is invalid for GCC
=======================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: : <!@TM:1538938424> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1538938424> | Writing default property annotation file C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\ao_control.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 190MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Oct  8 02:53:44 2018

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<!@TC:1538938419>
Map & Optimize Report


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<!@TC:1538938419>
# Mon Oct  8 02:53:44 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport8></a>Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1538938428> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1538938428> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1538938428> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1538938428> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -1.84ns		  18 /        14




Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1538938428> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 118MB peak: 190MB)

Writing Analyst data base C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\synwork\ao_control_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 190MB)

@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1538938428> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1538938428> | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 190MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 190MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1538938428> | Found inferred clock gw_con_top|tck_i with period 3.09ns. Please declare a user-defined clock on port tck_i.</font> 


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
<a name=pnr10></a># Timing Report written on Mon Oct  8 02:53:48 2018</a>
#


Top view:               gw_con_top
Requested Frequency:    323.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1538938428> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1538938428> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary11></a>Performance Summary</a>
*******************


Worst slack in design: -2.094

                     Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock       Frequency     Frequency     Period        Period        Slack      Type         Group                
--------------------------------------------------------------------------------------------------------------------------
gw_con_top|tck_i     323.1 MHz     137.3 MHz     3.095         7.282         -2.094     inferred     Autoconstr_clkgroup_0
System               100.0 MHz     NA            10.000        NA            NA         system       system_clkgroup      
==========================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





<a name=clockRelationships12></a>Clock Relationships</a>
*******************

Clocks                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
---------------------------------------------------------------------------------------------------------------------------
Starting          Ending            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack 
---------------------------------------------------------------------------------------------------------------------------
gw_con_top|tck_i  gw_con_top|tck_i  |  3.095       0.475  |  3.095       1.574  |  No paths    -      |  1.548       -2.094
===========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo13></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport14></a>Detailed Report for Clock: gw_con_top|tck_i</a>
====================================



<a name=startingSlack15></a>Starting Points with Worst Slack</a>
********************************

                               Starting                                                      Arrival           
Instance                       Reference            Type      Pin     Net                    Time        Slack 
                               Clock                                                                           
---------------------------------------------------------------------------------------------------------------
enable_reg[1]                  gw_con_top|tck_i     DFFNC     Q       enable_reg[1]          0.367       -2.094
enable_reg[0]                  gw_con_top|tck_i     DFFNC     Q       enable_reg[0]          0.367       -2.026
enable_reg[2]                  gw_con_top|tck_i     DFFNC     Q       enable_reg[2]          0.367       -1.817
tdi_d                          gw_con_top|tck_i     DFFNC     Q       control0_c[2]          0.367       -1.005
input_shift_reg[0]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[0]     0.367       0.475 
input_shift_reg[1]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[1]     0.367       0.475 
input_shift_reg[2]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[2]     0.367       0.475 
input_shift_reg[3]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[3]     0.367       0.475 
input_shift_reg[4]             gw_con_top|tck_i     DFFCE     Q       input_shift_reg[4]     0.367       0.475 
shift_dr_capture_dr_dly[0]     gw_con_top|tck_i     DFFC      Q       control0_c[4]          0.367       0.475 
===============================================================================================================


<a name=endingSlack16></a>Ending Points with Worst Slack</a>
******************************

                       Starting                                                           Required           
Instance               Reference            Type      Pin     Net                         Time         Slack 
                       Clock                                                                                 
-------------------------------------------------------------------------------------------------------------
input_shift_reg[0]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
input_shift_reg[1]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
input_shift_reg[2]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
input_shift_reg[3]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
input_shift_reg[4]     gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
module_id_reg[0]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
module_id_reg[1]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
module_id_reg[2]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
module_id_reg[3]       gw_con_top|tck_i     DFFCE     CE      enable_i_delay              1.415        -2.094
input_shift_reg[4]     gw_con_top|tck_i     DFFCE     D       input_shift_reg_ldmx[4]     1.415        -1.005
=============================================================================================================



<a name=worstPaths17></a>Worst Path Information</a>
<a href="C:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\ao_control.srr:srsfC:\Gowin\oled_ssd1306\impl\temp\gao\ao_control\rev_1\ao_control.srs:fp:22694:23198:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      1.548
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.415

    - Propagation time:                      3.508
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.093

    Number of logic level(s):                1
    Starting point:                          enable_reg[1] / Q
    Ending point:                            input_shift_reg[0] / CE
    The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
    The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

Instance / Net                   Pin      Pin               Arrival     No. of    
Name                   Type      Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
enable_reg[1]          DFFNC     Q        Out     0.367     0.367       -         
enable_reg[1]          Net       -        -       1.021     -           2         
enable_i_delay         LUT3      I1       In      -         1.388       -         
enable_i_delay         LUT3      F        Out     1.099     2.487       -         
enable_i_delay         Net       -        -       1.021     -           9         
input_shift_reg[0]     DFFCE     CE       In      -         3.508       -         
==================================================================================
Total path delay (propagation time + setup) of 3.641 is 1.599(43.9%) logic and 2.042(56.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1.548
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.415

    - Propagation time:                      3.508
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.093

    Number of logic level(s):                1
    Starting point:                          enable_reg[1] / Q
    Ending point:                            module_id_reg[0] / CE
    The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
    The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                 Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
enable_reg[1]        DFFNC     Q        Out     0.367     0.367       -         
enable_reg[1]        Net       -        -       1.021     -           2         
enable_i_delay       LUT3      I1       In      -         1.388       -         
enable_i_delay       LUT3      F        Out     1.099     2.487       -         
enable_i_delay       Net       -        -       1.021     -           9         
module_id_reg[0]     DFFCE     CE       In      -         3.508       -         
================================================================================
Total path delay (propagation time + setup) of 3.641 is 1.599(43.9%) logic and 2.042(56.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1.548
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.415

    - Propagation time:                      3.508
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.093

    Number of logic level(s):                1
    Starting point:                          enable_reg[1] / Q
    Ending point:                            module_id_reg[1] / CE
    The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
    The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                 Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
enable_reg[1]        DFFNC     Q        Out     0.367     0.367       -         
enable_reg[1]        Net       -        -       1.021     -           2         
enable_i_delay       LUT3      I1       In      -         1.388       -         
enable_i_delay       LUT3      F        Out     1.099     2.487       -         
enable_i_delay       Net       -        -       1.021     -           9         
module_id_reg[1]     DFFCE     CE       In      -         3.508       -         
================================================================================
Total path delay (propagation time + setup) of 3.641 is 1.599(43.9%) logic and 2.042(56.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      1.548
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.415

    - Propagation time:                      3.508
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.093

    Number of logic level(s):                1
    Starting point:                          enable_reg[1] / Q
    Ending point:                            module_id_reg[2] / CE
    The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
    The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                 Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
enable_reg[1]        DFFNC     Q        Out     0.367     0.367       -         
enable_reg[1]        Net       -        -       1.021     -           2         
enable_i_delay       LUT3      I1       In      -         1.388       -         
enable_i_delay       LUT3      F        Out     1.099     2.487       -         
enable_i_delay       Net       -        -       1.021     -           9         
module_id_reg[2]     DFFCE     CE       In      -         3.508       -         
================================================================================
Total path delay (propagation time + setup) of 3.641 is 1.599(43.9%) logic and 2.042(56.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      1.548
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.415

    - Propagation time:                      3.508
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -2.093

    Number of logic level(s):                1
    Starting point:                          enable_reg[1] / Q
    Ending point:                            module_id_reg[3] / CE
    The start point is clocked by            gw_con_top|tck_i [falling] on pin CLK
    The end   point is clocked by            gw_con_top|tck_i [rising] on pin CLK

Instance / Net                 Pin      Pin               Arrival     No. of    
Name                 Type      Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------
enable_reg[1]        DFFNC     Q        Out     0.367     0.367       -         
enable_reg[1]        Net       -        -       1.021     -           2         
enable_i_delay       LUT3      I1       In      -         1.388       -         
enable_i_delay       LUT3      F        Out     1.099     2.487       -         
enable_i_delay       Net       -        -       1.021     -           9         
module_id_reg[3]     DFFCE     CE       In      -         3.508       -         
================================================================================
Total path delay (propagation time + setup) of 3.641 is 1.599(43.9%) logic and 2.042(56.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 190MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 190MB)

---------------------------------------
<a name=resourceUsage18></a>Resource Usage Report for gw_con_top </a>

Mapping to part: gw1n_4lqfp144-6
Cell usage:
DFFC            1 use
DFFCE           9 uses
DFFNC           4 uses
GSR             1 use
INV             1 use
LUT2            3 uses
LUT3            6 uses
LUT4            5 uses

I/O ports: 17
I/O primitives: 17
IBUF           8 uses
OBUF           9 uses

I/O Register bits:                  0
Register bits not including I/Os:   14 of 3456 (0%)
Total load per clock:
   gw_con_top|tck_i: 15

@S |Mapping Summary:
Total  LUTs: 14 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 39MB peak: 190MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Mon Oct  8 02:53:48 2018

###########################################################]

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